Optimization of Photodetector Thickness in Vertically-Integrated Image Sensors

There is an emerging interest in vertically-integrated CMOS (VI-CMOS) image sensors. This trend arises from the difficulty in achieving high SNR, high dynamic range, and high frame rate with planar technologies while maintaining small pixel sizes, since the photodetector and electronics have to share the same pixel area and use the same technology. Fabrication methods for VI-CMOS image sensors add new degrees of freedom to the photodetector design. Having a model that gives a good approximation to the behavior of a device under different operating conditions is important for device optimization. This work presents a new approach in photodetector modeling, and uses it to optimize the thickness of the photosensitive layer in VI-CMOS image sensors. We consider a simplified structure of an a-Si:H photodetector, and develop analytical and numerical solutions, which are shown to be comparable, to state equations taken from semiconductor physics. If the photosensitive layer is too thin, our model shows that contact resistances dominate the device. If it is too thick, photogenerated carriers spread out too thinly and have little impact. Therefore, an optimum thickness can be found.